ath5k_hw_reg_read
ofdm_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1);
cck_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2);
pr_notice("ACK fail\t%d\n", ath5k_hw_reg_read(ah, AR5K_ACK_FAIL));
pr_notice("RTS fail\t%d\n", ath5k_hw_reg_read(ah, AR5K_RTS_FAIL));
pr_notice("RTS success\t%d\n", ath5k_hw_reg_read(ah, AR5K_RTS_OK));
pr_notice("FCS error\t%d\n", ath5k_hw_reg_read(ah, AR5K_FCS_FAIL));
pr_notice("tx\t%d\n", ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX));
pr_notice("rx\t%d\n", ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX));
pr_notice("busy\t%d\n", ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR));
pr_notice("cycles\t%d\n", ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE));
ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1));
ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2));
ath5k_hw_reg_read(ah, AR5K_OFDM_FIL_CNT));
ath5k_hw_reg_read(ah, AR5K_CCK_FIL_CNT));
ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
(ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
init_val = ath5k_hw_reg_read(ah, cur_reg);
cur_val = ath5k_hw_reg_read(ah, cur_reg);
cur_val = ath5k_hw_reg_read(ah, cur_reg);
return ath5k_hw_reg_read(ah, reg_offset);
ath5k_hw_reg_read(ah, r->addr));
v = ath5k_hw_reg_read(ah, AR5K_BEACON);
"AR5K_LAST_TSTP", ath5k_hw_reg_read(ah, AR5K_LAST_TSTP));
"AR5K_BEACON_CNT", ath5k_hw_reg_read(ah, AR5K_BEACON_CNT));
v = ath5k_hw_reg_read(ah, AR5K_TIMER0);
v = ath5k_hw_reg_read(ah, AR5K_TIMER1);
v = ath5k_hw_reg_read(ah, AR5K_TIMER2);
v = ath5k_hw_reg_read(ah, AR5K_TIMER3);
v = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
v = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
v = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL);
v = ath5k_hw_reg_read(ah, AR5K_PHY_RESTART);
v = ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ANT_DIV);
v = ath5k_hw_reg_read(ah, AR5K_PHY_ANT_SWITCH_TABLE_0);
v = ath5k_hw_reg_read(ah, AR5K_PHY_ANT_SWITCH_TABLE_1);
ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1),
ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1)));
ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2),
ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2)));
if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
ath5k_hw_reg_read(ah, AR5K_CR);
tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
ath5k_hw_reg_read(ah, AR5K_CR);
pending = ath5k_hw_reg_read(ah,
AR5K_REG_SM(ath5k_hw_reg_read(ah,
pending = ath5k_hw_reg_read(ah,
return ath5k_hw_reg_read(ah, tx_reg);
trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0;
ath5k_hw_reg_read(ah, AR5K_CR);
isr = ath5k_hw_reg_read(ah, AR5K_ISR);
pisr = ath5k_hw_reg_read(ah, AR5K_PISR);
sisr0 = ath5k_hw_reg_read(ah, AR5K_SISR0);
sisr1 = ath5k_hw_reg_read(ah, AR5K_SISR1);
sisr2 = ath5k_hw_reg_read(ah, AR5K_SISR2);
sisr3 = ath5k_hw_reg_read(ah, AR5K_SISR3);
sisr4 = ath5k_hw_reg_read(ah, AR5K_SISR4);
ath5k_hw_reg_read(ah, AR5K_PISR);
(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
ath5k_hw_reg_read(ah, AR5K_IER);
u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2)
ath5k_hw_reg_read(ah, AR5K_IER);
return ath5k_hw_reg_read(ah, AR5K_RXDP);
ath5k_hw_reg_read(ah, AR5K_ISR);
(ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio))
(ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio))
return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
*data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
(void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0);
atim = ath5k_hw_reg_read(ah, AR5K_TIMER3);
dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;
pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
srev = (ath5k_hw_reg_read(ah, AR5K_PHY(256)) >> 28) & 0xf;
srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) {
iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
} else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
s_seq[i] = ath5k_hw_reg_read(ah,
s_seq[0] = ath5k_hw_reg_read(ah,
tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
ath5k_hw_reg_read(ah, AR5K_RXDP);
staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
data = ath5k_hw_reg_read(ah, reg);
if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)