ath12k_pci_read32
ath12k_pci_read32(ab, ab->hw_params->otp_board_id_register);
val = ath12k_pci_read32(ab, MHISTATUS);
EXPORT_SYMBOL(ath12k_pci_read32);
.read32 = ath12k_pci_read32,
val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR);
val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab));
val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST(ab));
val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
reg, ab_pci->qmi_instance, ath12k_pci_read32(ab, reg));
u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset);
soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION);