ath10k_pci_write32
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
ath10k_pci_write32(ar, addr, val);
ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
ath10k_pci_write32(ar,
ath10k_pci_write32(ar,
ath10k_pci_write32(ar,
ath10k_pci_write32(ar,
ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);
ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);
.write32 = ath10k_pci_write32,
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);