ath10k_pci_read32
val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
val = ath10k_pci_read32(ar, addr);
return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
.read32 = ath10k_pci_read32,
val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);