and_phy_reg
and_phy_reg(pi, 0x44c,
and_phy_reg(pi, 0x4b0, ~((0x1 << 3) | (0x1 << 11)));
and_phy_reg(pi, 0x4f9, ~(0x1 << 3));
and_phy_reg(pi, 0x44d,
and_phy_reg(pi, 0x4b7, ~((0x7f << 8)));
and_phy_reg(pi, 0x4b1, ~((0x1 << 13)));
and_phy_reg(pi, 0x4fa, ~((0x1 << 3)));
and_phy_reg(pi, 0x43b,
void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
and_phy_reg(pi, 0x44c, (u16) ~((0x1 << 1) | (0x1 << 0)));
and_phy_reg(pi, 0x00a, ~(0x228));
and_phy_reg(pi, 0x6da, 0xFF7F);
and_phy_reg(pi, 0x44c, 0x0 >> 11);
and_phy_reg(pi, 0x43b, 0xC);
and_phy_reg(pi, 0x43b, ~(u16) ((0x1 << 1) | (0x1 << 4)));
and_phy_reg(pi, 0x44c,
and_phy_reg(pi, 0x44d,
and_phy_reg(pi, 0x4f9,
and_phy_reg(pi, 0x4fa,
and_phy_reg(pi, 0x453, 0xffff & ~(0x1 << 15));
and_phy_reg(pi, 0x44a, 0x7f);
and_phy_reg(pi, en_addr, ~en_mask);
and_phy_reg(pi, val_addr, ~val_mask);
and_phy_reg(pi, en_addr, ~en_mask);
and_phy_reg(pi, val_addr, ~val_mask);
and_phy_reg(pi, 0xec, ~field);
and_phy_reg(pi, 0xec, ~(0x1 << 0));
and_phy_reg(pi, 0x1e7, 0x7fff);
and_phy_reg(pi, 0x2ff, (u16)
and_phy_reg(pi, 0xa1, ~3);
and_phy_reg(pi, 0xa0, ~0x20);
and_phy_reg(pi, 0xa1, ~NPHY_RfseqMode_CoreActv_override);
and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
and_phy_reg(pi, 0x78, RFCC_OE_POR_FORCE);
and_phy_reg(pi, 0x342, ~(0x1 << 1));
and_phy_reg(pi, 0x78, ~RFCC_POR_FORCE);
and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
and_phy_reg(pi, 0x09, ~NPHY_BandControl_currentBand);
and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
and_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_TEST, ~0x840);
and_phy_reg(pi, 0xa0, ~BPHY_BAND_SEL_UP20);
and_phy_reg(pi, 0x310,
and_phy_reg(pi, 0xc2, 0x7FFF);
and_phy_reg(pi, 0xc2,
and_phy_reg(pi, 0xc3, (u16) ~(0x1 << 2));
and_phy_reg(pi, 0xbf, (u16) (~(0x1f << 0)));
and_phy_reg(pi, 0x1e7,
and_phy_reg(pi, 0x1e7,
and_phy_reg(pi, 0x8f, ~(0x1 << 8));
and_phy_reg(pi, 0xa5, ~(0x1 << 8));
and_phy_reg(pi, 0xa5, ~(0x1 << 14));