drivers/gpu/drm/armada/armada_crtc.c

354

armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);

drivers/gpu/drm/armada/armada_crtc.c

379

armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);

drivers/gpu/drm/armada/armada_crtc.c

380

armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);

drivers/gpu/drm/armada/armada_crtc.c

381

armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);

drivers/gpu/drm/armada/armada_crtc.c

382

armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,

drivers/gpu/drm/armada/armada_overlay.c

104

armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);

drivers/gpu/drm/armada/armada_overlay.c

107

armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);

drivers/gpu/drm/armada/armada_overlay.c

110

armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);

drivers/gpu/drm/armada/armada_overlay.c

119

armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),

drivers/gpu/drm/armada/armada_overlay.c

121

armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1),

drivers/gpu/drm/armada/armada_overlay.c

123

armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2),

drivers/gpu/drm/armada/armada_overlay.c

125

armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),

drivers/gpu/drm/armada/armada_overlay.c

127

armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1),

drivers/gpu/drm/armada/armada_overlay.c

129

armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2),

drivers/gpu/drm/armada/armada_overlay.c

134

armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);

drivers/gpu/drm/armada/armada_overlay.c

137

armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);

drivers/gpu/drm/armada/armada_overlay.c

182

armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);

drivers/gpu/drm/armada/armada_overlay.c

186

armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);

drivers/gpu/drm/armada/armada_overlay.c

188

armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);

drivers/gpu/drm/armada/armada_overlay.c

197

armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);

drivers/gpu/drm/armada/armada_overlay.c

201

armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);

drivers/gpu/drm/armada/armada_overlay.c

205

armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);

drivers/gpu/drm/armada/armada_plane.c

167

armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);

drivers/gpu/drm/armada/armada_plane.c

170

armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);

drivers/gpu/drm/armada/armada_plane.c

173

armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);

drivers/gpu/drm/armada/armada_plane.c

178

armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),

drivers/gpu/drm/armada/armada_plane.c

180

armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),