drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h

5665

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h

10016

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h

3609

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h

6260

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h

2813

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h

2813

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h

7894

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_sh_mask.h

7873

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_6_0_sh_mask.h

4053

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h

3172

#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L