Symbol: DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
43769
#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
49005
#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
29371
#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
30578
#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h
30864
#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h
678
#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1