drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43634

#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

48870

#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

29256

#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

30463

#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30732

#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

546

#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18372

#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20612

#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21220

#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10