drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43600

#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

48836

#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

29225

#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

30432

#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30705

#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

519

#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18360

#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20598

#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21204

#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2