drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43601

#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

48837

#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

29226

#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

30433

#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30706

#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

520

#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18362

#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20600

#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21206

#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4