drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43911

#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

49147

#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

29517

#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

30719

#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30952

#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

805

#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18415

#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20665

#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21275

#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000