drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43874

#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

49110

#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

29480

#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

30682

#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30922

#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

775

#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18404

#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20652

#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21260

#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2