drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43070

#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

48310

#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

28740

#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

29956

#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30278

#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

30

#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18272

#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20490

#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21092

#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2