drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43071

#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

48311

#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

28741

#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

29957

#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30279

#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

31

#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18274

#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20492

#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21094

#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4