drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43381

#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

48621

#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

29032

#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

30243

#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30525

#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

316

#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18327

#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20557

#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21163

#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000