drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43344

#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

48584

#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

28995

#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

30206

#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30495

#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

286

#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18316

#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20544

#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21148

#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2