drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

43345

#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

48585

#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

28996

#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

30207

#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

30496

#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

287

#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

18318

#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

20546

#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

21150

#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4