drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20284

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18456

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17350

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19589

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14044

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13250

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13016

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x01FFFFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12873

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14173

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14038

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

3969

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16403

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3325

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3933

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4455

#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff