drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20301

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18473

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17367

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19606

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14061

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13267

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13033

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12890

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14190

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14055

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

3986

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16420

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3340

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3954

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4476

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0