drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20324

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00030000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12914

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14214

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14079

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

4011

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16445

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3343

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x30000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3959

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4481

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000