drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

6706

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

6972

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

6570

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

7345

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

3723

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

7011

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

9203

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

1218

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

1117

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

1084

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

1717

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

1134

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

2847

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3082

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3696

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4218

#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10