drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

17839

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

16099

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

15336

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

17491

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

12152

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

11805

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

11380

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

10917

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

12394

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

12198

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

2214

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

13925

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

1753

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

2277

#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc