drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

17883

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

16145

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

15384

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

17539

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

12200

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

10953

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

12430

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

12234

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

2250

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

13961

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

2758

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

1131

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

1447

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

1971

#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff