drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c

36

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20474

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18644

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17594

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19839

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14288

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13485

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13257

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

13055

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14355

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14220

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

4153

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16589

#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8