drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

18180

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

16531

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

11217

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

12694

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

12492

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

2601

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

14312

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

2598

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

1435

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

1879

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

2401

#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1