drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

18023

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

16287

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

11078

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

12555

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

12359

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

2375

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

14086

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

2430

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

1233

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

1573

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

2097

#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000