drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20288

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18460

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17354

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19593

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14048

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13254

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13020

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12877

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14177

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14042

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

3973

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16407

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3328

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3940

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4462

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2