drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20295

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18467

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17361

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19600

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14055

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13261

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13027

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12884

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14184

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14049

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

3980

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16414

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3327

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3939

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4461

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc