drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20286

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18458

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17352

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19591

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14046

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13252

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13018

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12875

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14175

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14040

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

3971

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16405

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3936

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4458

#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0