drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20308

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18479

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17373

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19612

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14067

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13273

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13040

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12901

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14201

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14066

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

3998

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16432

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3968

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4490

#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19