drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20304

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18476

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17370

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19609

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14064

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13270

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13036

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12893

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14193

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14058

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

3989

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16423

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3342

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3956

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4478

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8