drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20321

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18492

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17387

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19626

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14081

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13286

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13053

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12910

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14210

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14075

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

4007

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16441

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3341

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3955

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4477

#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00