drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20318

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18489

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17384

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19623

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14078

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13283

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13050

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12907

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14207

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14072

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

4004

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16438

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3339

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3953

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4475

#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f