drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20316

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18487

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17382

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19621

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14076

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13281

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13048

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12905

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14205

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14070

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

4002

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16436

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3360

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3976

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4498

#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e