drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20317

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18488

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17383

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19622

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14077

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13282

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13049

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12906

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14206

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14071

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

4003

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16437

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3362

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3978

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4500

#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f