drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20307

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12897

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14197

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14062

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

3993

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16427

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3344

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3960

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4482

#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11