drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20346

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18516

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

17412

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

19651

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

14106

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

13310

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

13078

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

12935

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14235

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14100

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

4033

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

16467

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

3372

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

3988

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

4510

#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14