drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

3667

#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

56027

#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

33931

#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

39857

#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h

75293

#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h

101563

#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

44506

#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

3677

#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L