drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

3705

#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

56044

#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

33948

#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

39871

#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h

75307

#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h

101580

#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

44523

#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

3694

#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L