drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

3681

#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

56034

#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

33938

#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

39862

#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h

75298

#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h

101570

#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

44513

#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

3684

#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L