drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

3665

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

56026

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

33930

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

39856

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h

75292

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h

101562

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

44505

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

3676

#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L