drivers/gpu/drm/amd/amdgpu/vi.c

102

#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

56046

#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

33950

#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

39873

#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h

75309

#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h

101582

#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

44525

#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

3696

#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L