CLK_TOP_SYSPLL_D5

include/dt-bindings/clock/mediatek,mt6735-topckgen.h

14

#define CLK_TOP_SYSPLL_D5 7

include/dt-bindings/clock/mediatek,mt6795-clk.h

59

#define CLK_TOP_SYSPLL_D5 48

include/dt-bindings/clock/mediatek,mt8365-clk.h

25

#define CLK_TOP_SYSPLL_D5 15

include/dt-bindings/clock/mt2701-clk.h

14

#define CLK_TOP_SYSPLL_D5 4

include/dt-bindings/clock/mt2712-clk.h

44

#define CLK_TOP_SYSPLL_D5 13

include/dt-bindings/clock/mt6765-clk.h

45

#define CLK_TOP_SYSPLL_D5 10

include/dt-bindings/clock/mt6797-clk.h

56

#define CLK_TOP_SYSPLL_D5 46

include/dt-bindings/clock/mt7622-clk.h

36

#define CLK_TOP_SYSPLL_D5 24

include/dt-bindings/clock/mt7629-clk.h

42

#define CLK_TOP_SYSPLL_D5 32

include/dt-bindings/clock/mt8135-clk.h

41

#define CLK_TOP_SYSPLL_D5 30

include/dt-bindings/clock/mt8173-clk.h

61

#define CLK_TOP_SYSPLL_D5 51

include/dt-bindings/clock/mt8183-clk.h

81

#define CLK_TOP_SYSPLL_D5 45

scripts/dtc/include-prefixes/dt-bindings/clock/mediatek,mt6735-topckgen.h

14