CLK_MM_DISP_WDMA0
#define CLK_MM_DISP_WDMA0 21
#define CLK_MM_DISP_WDMA0 55
#define CLK_MM_DISP_WDMA0 21
#define CLK_MM_DISP_WDMA0 11
#define CLK_MM_DISP_WDMA0 25
#define CLK_MM_DISP_WDMA0 22
#define CLK_MM_DISP_WDMA0 21
#define CLK_MM_DISP_WDMA0 24
#define CLK_MM_DISP_WDMA0 5
#define CLK_MM_DISP_WDMA0 5
#define CLK_MM_DISP_WDMA0 21
#define CLK_MM_DISP_WDMA0 55
#define CLK_MM_DISP_WDMA0 21
#define CLK_MM_DISP_WDMA0 11
#define CLK_MM_DISP_WDMA0 25
#define CLK_MM_DISP_WDMA0 22
#define CLK_MM_DISP_WDMA0 21
#define CLK_MM_DISP_WDMA0 24
#define CLK_MM_DISP_WDMA0 5
#define CLK_MM_DISP_WDMA0 5