drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h

4123

#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h

4111

#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h

3329

#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h

4245

#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h

3943

#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00

drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h

884

#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L

drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h

357

#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L

drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h

838

#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L