drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h

145

#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x00000000

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h

4148

#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h

4136

#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h

3354

#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h

4270

#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h

3968

#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h

906

#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h

379

#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h

860

#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0