drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h

144

#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h

4147

#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h

4135

#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h

3353

#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h

4269

#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h

3967

#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff

drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h

907

#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h

380

#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL

drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h

861

#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL