drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h

122

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h

4103

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h

4091

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h

3307

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h

4223

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000

drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h

3891

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000

drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h

446

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L

drivers/gpu/drm/amd/include/asic_reg/thm/thm_13_0_2_sh_mask.h

822

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L

drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h

327

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L

drivers/gpu/drm/amd/include/asic_reg/thm/thm_15_0_0_sh_mask.h

144

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x3FF00000L

drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h

803

#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L