drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

89

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1534

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1537

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2975

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

2071

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6375

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7191

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6208

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5385

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

840

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L